JFET Construction and Working

The junction field-effect transistor (JFET) is a three element electronic device. Its operation is based on the conduction of current carriers through a single piece of semiconductor material. This piece of material is called the channel. An additional piece of semiconductor material is diffused into the channel. This element is called the gate.

The entire unit is built on a third piece of semiconductor known as the substrate. The assembled device is housed in a package. The physical appearance of a JFET in its housing is very similar to that of a bipolar transistor.

N-Channel JFET Construction and Working

Its construction has a thin channel of N material formed on the P substrate. The P material of the gate is then formed on top of the N channel. Lead wires are attached to each end of the channel and the gate. No connection is made to the substrate of this device.

The schematic symbol of an N-channel JFET is somewhat representative of its construction. The bar part of the symbol refers to the channel. The drain (D) and source (S) are attached to the channel. The gate (G) has an arrow. This shows that it forms a P-N junction.

The arrowhead of an N-channel symbol “Points iN” toward the channel. This indicates that it is a P-N junction. The arrowhead or gate is P material and the channel N material. This part of the device responds as a junction diode.

The operation of a JFET is somewhat unusual when compared with that of a bipolar transistor. Figure 3-51 shows the source and drain leads of a JFET connected to a dc voltage source. In this case, maximum current will flow through the channel.

The I_S and I_D meters will show the same amount of current. The value of V_DD and the internal resistance of the channel determines the amount of channel current flow. Typical source-drain resistance values of a JFET are several hundred ohms. Essentially this means that full conduction will take place in the channel even when the gate is open.

A JFET is considered to be a normally on device. Current carriers passing through the channel of a JFET are controlled by the amount of bias voltage applied to the gate.

In normal circuit operation, the gate is reverse biased with respect to the source. Reverse biasing of the gate-source of any P-N junction will increase the size of its depletion region. In effect, this will restrict or deplete the number of majority carriers that can pass through the channel. This means that drain current (I_D) is controlled by the value of V_GS.

If V_GS becomes great enough, no I_D will be permitted to flow through the channel. The voltage that causes this condition is called the cutoff voltage I_D can be controlled anywhere between full conduction and cutoff by a small change in gate voltage.

P-Channel JFET Construction and Working

The crystal structure, element names, and schematic symbol of a P-channel JFET are shown in Figure 3-52. This device has a thin channel of P material formed on an N substrate. The N material of the gate is then formed on top of the P channel. Lead wires are attached to each end of the channel and to the gate. Other construction details are the same as those of the N-channel device.

The schematic symbol of a JFET is different only in the gate element. In a P-channel device the arrow is “Not Pointing” toward the channel. This means that the gate is N material and the channel is P material.

In conventional operation, the gate is made positive with respect to the source. Varying values of reverse bias gate voltage will change the size of the P-N junction depletion zone. Current flow through the channel can be altered between cutoff and full conduction.

P-channel and N-channel JFETs cannot be used in a circuit without a modification in the source voltage polarity.

JFET Characteristic Curves

The JFET is a very unique device compared with other solid-state components. A small change in gate voltage will, for example, cause a substantial change in drain current. The JFET is therefore classified as a voltage-sensitive device. By comparison, bipolar transistors are classified as current-sensitive devices.

A JFET has a rather unusual set of characteristics compared with other solid-state devices. A family of JFET characteristic curves is shown in above Figure. The horizontal part of the graph shows the voltage appearing across the source-drain as V_DS. The vertical axis shows the drain current (I_D) in milli-amperes.

Individual curves of the graph show different values of gate voltage (V_GS). The cutoff voltage of this device is approximately –7 V. The control range of the gate is from 0 to –6 V. A drain family of characteristic curves tells a great deal about the operation of a JFET.

Refer to point A on the –3 V_GS curve. If the device has –3 V applied to its gate and a V_DS of 6 V, there is approximately 4 mA of I_D flowing through the channel. This is determined by projecting a line to the left of the intersection of –3 V_GS and 6 V_DS.

Any combination of I_D, V_GS, and V_DS can be determined from the family of curves.

Developing JFET Characteristic Curves

A special circuit is used to develop the data for a drain family of characteristic curves. Above Figure shows a circuit that is used to find the data points of a characteristic curve for an N-channel JFET. Three meters are used to monitor this data.

• Gate voltage is monitored by a V_GS meter connected between the gate-source leads.
• Drain current is measured by a milli-ampere meter connected in series with the drain.
• V_DS is measured with a voltmeter connected across the source and drain.
• V_GS and V_DS are adjusted to different values while monitoring I_D.
• Two variable dc power supplies are used in the test circuit. The data points of a single curve are developed by first adjusting V_GS to 0 V.
• V_DS is then adjusted through its range starting at 0 V. Normally, V_DS is increased in 0.1-V steps up to 1 V.
• I_D increases very quickly during this operational time.
• V_DS is then increased in 1-V steps recording the I_D values.
• Corresponding I_D and V_GS values are then plotted on a graph as the 0 V_GS curve.

To develop the second curve, V_DS must be returned to zero.

• V_GS is then adjusted to a new value. 0.5 V would be a suitable value for most JFETs.
• V_DS is again adjusted through its range while monitoring _ID.
• Data for the second curve are then recorded on the graph.

To obtain a complete family of drain curves, the process would be repeated for several other V_GS values. A typical family of curves may have 8 to 10 different values.

The step values of V_DS, V_GS, and I_D will obviously change with different devices. Full conduction is usually determined first. This gives an approximation of representative I_D and V_DS values.

Normally, I_D will level off to a rather constant value when V_DS is increased. V_DS can be increased in value to a point where I_D starts a slight increase. Generally, this indicates the beginning of the breakdown region. JFETs are usually destroyed if conduction occurs in this area of operation.

Maximum V_DS values for a specific device are available from the manufacturer. It is a good practice to avoid operation in or near the breakdown region of the device.

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