Digital Electronics

Microcontroller Architecture

Microcontroller Architecture

Microcontroller architecture may be defined in several ways. These include architecture used by the processor to access memory, architecture used for mapping special-function registers into memory space and the processor architecture itself.

Architecture to Access Memory

There are two fundamental architectures used by the processing units to access memory, namely Von Neumann architecture and Harvard architecture.

Von Neumann architecture uses a single memory to hold both program instructions and data. There is one common data and address bus between processor and memory (Fig. 1).

Fig. 1

Instructions and data are fetched in sequential order, thus limiting the operation data transfer rate or the throughput. This phenomenon is commonly referred to as the Von Neumann bottleneck. The throughput is very small compared with the size of the memory.

In present-day machines, the throughput is also very small compared with the rate at which the processor itself can work. In the condition where the processor is required to perform minimal processing on large amounts of data, the processor is forced to wait for vital data to be transferred from or to memory. Microcontroller type number 68HC11 uses Von Neumann architecture.

Harvard architecture uses physically separate memories for program instructions and data. It therefore requires separate buses for program and data, as shown in Fig. 2.

Fig. 2

In such architecture, instructions and operands can be fetched simultaneously, which makes microcontrollers using this architecture much faster compared with the ones using Von Neumann architecture.

Also, different data and program bus widths are possible, which allows the program and data memory to be better optimized to architectural requirements.

In fact, the word width, timing, implementation technology and memory address structure can be different in the two cases. Program memory is usually much larger than data memory, which implies that the address bus for the program memory is wider than the address bus for the data memory.

Mapping Special-Function Registers into Memory Space

There are again two fundamental architectures used for mapping special-function registers into memory space.

Fig. 3(a)

In the first type of arrangement, I/O space and memory space are separated as shown in Fig. 3(a). I/O devices have a separate address space, which is accomplished by either an extra I/O pin on the CPU physical interface or through a dedicated I/O bus.

As a result of this, access to I/O control registers requires special instructions. It is particularly attractive in CPUs having a limited addressing capability. It is generally found on Intel microprocessors.

In the second arrangement, called the memory-mapped I/O, I/O control registers are mapped into memory address space as shown in Fig. 3(b).

Fig. 3(b)

Read and write operations to the control registers are done via absolute memory addresses, which could be variables at absolute addresses or pointers to absolute addresses in high-level languages. In this case, no special instructions are needed to access I/O control registers. The memory-mapped I/O uses the same bus to address both memory and I/O devices. CPU instructions used to read from or write to memory are also used in accessing I/O devices.

Processor Architecture

Processor architecture can be categorized as one of the following four architectures: accumulator-based architecture, register-based architecture, stack-based architecture and pipeline architecture.

1. Accumulator-based Architecture

In accumulator-based architecture, as shown in Fig. 4, instructions begin and end in accumulators (Acc A and Acc B in Fig. 4), which are specially designated registers.

Fig. 4

In a typical operation, one of the operands is found in the accumulator and the other is to be fetched from memory. The result of the operation is placed in the accumulator.

As one of the operands needs to be continually fetched from memory, this architecture is slower than the register-based and stack-based architectures. However, accumulator-based architecture has the ability to run fairly complicated instructions.

2. Register-based Architecture

In register-based architecture, as shown in Fig. 5, both operands are stored in registers and the result of operation is also stored in a register. The registers are typically colocated with the processor.

Microcontroller Architecture
Fig. 5

Since the processor and registers operate at the same speed, this architecture is much faster than the previously discussed accumulator-based architecture. The contents of the register are read from and written to memory using background operation.

3. Stack-based Architecture

In stack-based architecture, both operands and the operation to be performed are stored on the stack, which could be configured around dedicated registers or a special portion of RAM. The result of operation is placed back on the stack.

Fig. 6

Figure 6 shows typical block schematic arrangement of this type of architecture.

4. Pipeline Architecture

In pipelined architecture, as shown in Fig. 7, there are separate hardware stages for execution of different steps involved in execution of an instruction.

Fig. 7

These different steps include fetching an instruction from memory, decoding the instruction, fetching instruction operands from memory or registers, executing the instruction and then finally placing the result back on the memory.

Pipelining allows these stages to overlap and perform with parallelism. The overall result is that the execution of an instruction is completed on every clock cycle.

Instructions in a pipelined architecture are usually simple instructions that can be implemented within a single stage. These simple instructions act as building blocks for more complex instructions.

Power-Saving Modes

Power consumption is one of the important issues in battery-powered devices. Most microcontrollers come with various power-saving features. For a given application requirement, designers use these features to keep the power consumption down to an optimum value without compromising the operational requirements of the device. It may be mentioned here that not all modes are for power saving.

Some microcontrollers support in-circuit debugging. As an example, some of the power-saving modes available with the 80C51 family of microcontrollers are briefly outlined in the following paragraphs. The stop clock mode allows the clock oscillator to be stopped or the clock speed to be reduced to as low as 0 MHz.

When the oscillator is stopped, the special-function registers and RAM retain their values. This mode allows reduced power consumption by lowering the clock frequency to any value.

The idle mode is another power-saving mode available with the 80C51 family of microcontrollers. In this mode, the processor puts itself to sleep while all on-chip peripheral components stay active. The processor contents, the on-chip RAM and all special-function registers remain intact during the idle mode.

The instruction that invokes this mode is the last instruction executed in the normal operating mode before the idle mode is activated. The idle mode can be terminated by either an enabled interrupt or by a hardware reset.

By an enabled interrupt, the process is picked up at the interrupt service routine and continued. Hardware reset starts the processor in the same manner as it does on a power-on reset.

The power down mode is recommended for the lowest power consumption. When this mode is enabled, the oscillator stops and the instruction that invokes the power down mode is the last instruction executed. Special-function registers and on-chip RAM retain their values down to a VCC amplitude of 2.0 V. VCC must be brought to the minimum specified operating voltage before this mode is deactivated.

Either a hardware reset or an external interrupt can be used to terminate the power down mode. While a hardware reset redefines all the special-function registers and retains on-chip RAM values, an external interrupt allows both special-function registers and the on-chip RAM to retain their values.

For proper termination of the power-down mode, a reset or external interrupt should not be executed unless VCC is restored to its normal operating level and also has been held active long enough for the oscillator to start and stabilize.

Yet another mode available with the 80C51 family of microcontrollers that helps in power saving is the LPEP. The EPROM array contains some analogue circuits that are not required for a VCC of less than 4.0 V. This feature can be used to save power by setting the LPEP bit, resulting in reduced supply current. This mode should be used only for applications that require a VCC of less than 4.0 V

Application-Relevant Information

This section briefly presents application-relevant information in terms of general specifications, microcontroller-related features and peripheral features on some of the common types of microcontroller from well-known international manufacturers including Intel, Freescale Semiconductor, Microchip Technology, Altera, Atmel, Zilog, Lattice Semiconductor, National Semiconductor, Applied Micro Circuits Corporation (AMCC), Fujitsu, Infineon, Dallas Semiconductor, Philips Semiconductors, Texas Instruments, Xilinx, NEC, Toshiba and so on.

Some of the more widely used type numbers, including the 80C51 family of microcontrollers (Intel and many more manufacturers), the 89C51 microcontroller (Intel and many more manufacturers), the 68HC11 family of microcontrollers (Freescale Semiconductor) and the PIC 16X84 family of microcontrollers (Microchip Technology), are discussed in a little more detail. For these type numbers, information such as architecture, pin connection diagrams, functional description of different pins, addressing modes, etc., is also presented.

Eight-Bit Microcontrollers

This subsection outlines salient features of popular eight-bit microcontrollers. For most of the type numbers, the information is contained under two headings, namely microcontroller-related features and peripheral-related features.

1. 80C51/87C51/80C31 (Dallas Semiconductor and Other Manufacturers)

Microcontroller-related Features: MCS-51 architecture, CMOS technology, 4K × 8 ROM (no ROM in 80C31), 128 × 8 RAM, memory addressing capability of 64K (ROM and RAM), special-function registers, six interrupt sources, three power control modes including STOP CLOCK, IDLE and POWER DOWN modes, two clock speed ranges of 0–16 MHz and 0–33 MHz, low EMI (inhibit ALE) and three package style options (40-pin dual in-line, 44-pin plastic leaded chip carrier and 44-pin plastic quad flat pack).

Peripheral-related Features: Two 16-bit counters/timers, four eight-bit I/O ports and full duplex-enhanced UART.

Fig. 9

Fig. 9 shows the pin connection diagram in the 40-pin dual in-line package.

Registers: Registers are categorized as general-purpose registers and special-function registers. The 80C51 family of microcontrollers has an accumulator, B-register and four register banks, each having eight-bit wide registers R0 to R7. Registers R0 through R7 are used as scratch-pad registers. In addition, there is an eight-bit wide stack pointer and a 16-bit wide program counter. Special-function registers include program status word (PSW), data pointer (DPTR), timer registers, control registers and capture registers.

Addressing Modes: The 80C51 family of microcontrollers supports five addressing modes including register addressing, direct addressing, register indirect addressing, immediate addressing and base register plus index register addressing.

Instruction Set: The instruction set of the 80C51 family of microcontrollers consists of 111 instructions divided into five categories, namely data transfer instructions, arithmetic instructions, logical instructions, Boolean variable manipulation instructions and control transfer instructions.

Interrupts: The 80C51 family of microcontrollers supports five vectored interrupts. These include external interrupt 0, external interrupt 1, timer/counter 0 interrupt, timer/counter 1 interrupt and serial port interrupts.

Power Modes: The 80C51 family of microcontrollers offers various operational modes that can be used to reduce power consumption. These include STOP CLOCK MODE which enables the clock speed to be reduced down to 0 MHz, IDLE MODE when the CPU puts itself to sleep while all of the on-chip peripherals stay active and POWER DOWN MODE in which the oscillator is stopped. In addition to the powersaving operational modes, it also offers ONCETM (On-Circuit Emulation) MODE which facilitates in-circuit testing and debugging.

2. 80C31FA/8XC51FA/FB/FC (Dallas Semiconductor and Other Manufacturers) The same as 80C51 except for the size of ROM and RAM, which is 0K/8K/16K/32K (ROM) and 256 bytes (RAM)

3. 80C31RA+/8XC51RA+/RB+/RC+(Dallas Semiconductor and Other manufacturers) The same as 80C51 except for the size of ROM and RAM, which is 0K/8K/16K/32K (ROM) and 512 bytes (RAM).

4. 8XC51RD+(Dallas Semiconductor and Other Manufacturers) The same as 80C51 except for the size of ROM and RAM, which is 64K (ROM) and 1024 bytes (RAM).

5. 80C32/8XC52/54/58 (Dallas Semiconductor and Other Manufacturers) The same as 80C51 except for the size of ROM and RAM, which is 0K/8K/16K/32K (ROM) and 256 bytes (RAM).

6. 89C51 (ATMEL and Other Manufacturers)

Microcontroller-related Features: MCS-51 architecture, CMOS technology, 4K × 8 of in-system reprogrammable ROM, 128 × 8 internal RAM, memory addressing capability of 64K (ROM and RAM), special-function registers, six interrupt sources, two power-saving modes (IDLE and POWER DOWN modes), a clock speed range of 0–24 MHz, low EMI (inhibit ALE), three package style options (40-pin dual in-line, 44-pin plastic leaded chip carrier and 44-pin plastic quad flat pack) and compatible with the industry-standard MCS-51 instruction set and pin-out.

Peripheral-related Features: Two 16-bit counters/timers, 32 programmable I/O lines and a programmable serial channel.

Pin connection diagram are the same as those given earlier for the case of the 80C51 family of microcontrollers in Fig. 9.

7. 68HC05 Family of Microcontrollers (Freescale Semiconductor)

Microcontroller-related Features: Fully static chip design using a standard eight-bit M68HC05 core, a clock speed of 4 MHz, 920 bytes of on-chip RAM, 32K of ROM, 7932 bytes of EEPROM (maximum values across the family of devices), power-saving WAIT mode and available in 40-pin DIP and 42-pin SDIP package styles.

Peripheral-related Features: Two serial interface channels, a multifunction timer with periodic interrupt, eight A/D converter channels, three PWM channels and 80 I/O lines (maximum values across the family of devices).

8. 68HC11 Family of Microcontrollers (Freescale Semiconductor)

Microcontroller-related Features: Fully static chip design using an eight-bit M68HC11 core, a clock speed of 5 MHz, 0/256/512/768/1024 bytes of on-chip RAM (in different variants), 0/12/20 kB of on-chip ROM or EPROM (in different variants), 0/512/2048 bytes of on-chip EEPROM (in different variants), power-saving STOP and WAIT modes and available in six different package styles.

Peripheral-related Features: Asynchronous non-return-to-zero (NRZ) serial communication interface (SCI), synchronous serial peripheral interface (SPI), eight-channel, eight-bit analogue-to-digital converter, 16-bit timer system including three input capture channels, four output compare channels and an additional channel configurable as an input or an output channel, eight-bit pulse accumulator and 38 general-purpose I/O pins including 16 bidirectional I/O pins, 11 input-only pins and 11 output-only pins.

Fig. 10

Pin connection diagrams are shown in Fig. 10 (56-pin SDIP package) and Fig. 11 (48-pin DIP package). DIP and SDIP respectively stand for dual in-line package and shrink dual in-line package.

Fig. 11

9. PIC 16X84 Family of Microcontrollers (Microchip Technology)

PIC 16C84 and PIC 16F84 are the two microcontrollers in the PIC 16X84 family of microcontrollers from Microchip Technology. PIC 16F84 is an improved version of PIC 16C84.

Microcontroller-related Features: High-performance RISC CPU, 14-bit wide instructions, eight-bit wide data path, 1024 × 14 EEPROM program memory, 64 bytes of on-chip data EEPROM, 36 × 8 general-purpose registers (16C84), 68 bytes of data RAM (16F84), 15 special-function hardware registers (16F84), a clock speed of 10/20 MHz (16C84/16F84), direct, indirect and relative addressing modes, power-saving SLEEP mode and four interrupt sources.

Peripheral-related Features: Thirteen I/O pins with individual direction control, high current sink/source for direct LED drive and eight-bit timer/counter with an eight-bit programmable prescaler.

Fig. 12

Figure 12 shows the pin connection diagram in the 18-pin DIP package.

10.   XC-800 Family of Microcontrollers (Infineon)

The XC-800 family of microcontrollers offers high-performance eight-bit microcontrollers, with some of the members providing advanced networking capabilities by integrating both a CAN controller and LIN support on a single chip. Salient features of two of its members, i.e. XC-886/888 and XC-866, are briefly outlined in the following paragraphs.

Microcontroller-related Features: High-performance XC-800 core based on industry-standard 8051 architecture, a clock speed of 24 MHz, 24K or 32K of flash memory (XC-886/888), 256 bytes of RAM and 1536 bytes of XRAM (XC-886/888), 256 bytes of RAM and 512 bytes of XRAM (XC-866) and four power-saving modes including SLOW DOWN mode, IDLE mode, POWER DOWN mode and clock gating control.

Peripheral-related Features: Total of 34/48 general-purpose I/O ports, including eight analogue ports (XC-886/888) and 27 general purpose I/O ports (XC-866), eight-channel, 10-bit analogue-to-digital converter, four 16-bit general purpose timers (XC-886/888) and three 16-bit timers (XC-866), programmable 16-bit watchdog timer (WDT), two UARTs, including one for LIN simulation (XC-886/888) and one for LIN simulation, and one serial peripheral interface (XC-866).

16-Bit Microcontrollers

This subsection outlines salient features of some of the popular 16-bit microcontrollers. Again, the information is mainly contained under the headings microcontroller-related features and peripheral related features.

1. 68HC12 Family of Microcontrollers (Freescale Semiconductor)

Microcontroller-related Features: High-performance 16-bit CPU12 core having a 20-bit ALU, upward compatibility with the 68HC11 microcontroller instruction set, enhanced indexed addressing and fuzzy logic instructions, 1024 bytes of RAM, 32K of flash EEPROM and 768 bytes of EEPROM, a clock speed of 8 MHz, slow-mode clock divider, computer operating properly (COP) watchdog timer and available in 80-pin QFP and 112-pin TQFP packages.

Peripheral-related Features: Eight-channel, 10-bit analogue-to-digital converter, eight-channel, 16-bit input capture or output compare channels, up to 63 I/O lines, 16-bit pulse accumulator, eight-bit/four-channel or 16-bit/two channel pulse width modulator, asynchronous serial communication interface (SCI) and synchronous serial peripheral interface (SPI).

2. 68HC16 Family of Microcontrollers (Freescale Semiconductor)

The 68HC16 family of microcontrollers is the 16-bit enhancement of the eight-bit 68HC11 family of microcontrollers. This family of microcontrollers has been designed to provide many powerful features without the need for CPU intervention.

Microcontroller-related Features: 8K of ROM, 4K of RAM, clock speeds of 16, 20 and 25 MHz and available in 132-pin PQFP and 144-pin LQFP packages.

Peripheral-related Features: Twenty-four I/O lines, general-purpose timer, asynchronous serial communication interface (SCI) and synchronous serial peripheral interface (SPI).

32-Bit Microcontrollers

This subsection outlines salient features of some of the popular 32-bit microcontrollers. The families of microcontrollers that are briefly described in the following paragraphs include 683XX, MCORE, MPC500 and MCFXXX families (Freescale), the LPC-3000 family (Philips Semiconductors) and the TRICORE family (Infineon).

1. 683XX Family of Microcontrollers (Freescale Semiconductors)

Different members of this family include 68302, 68306, 68331/332/336, 68340, 68360 and 68375/376. 68302 uses an integrated multiprotocol processor. All other members of the family use a CPU32 core. The CPU32 core is a 32-bit processing unit based on the 68000 software model and instruction set with some additional features from 68010 and 68020. It also has some new features added to the core for control operations.

Salient features of this family of microcontrollers are as follows. The family offers 10K of RAM, 256K of flash, a clock speed of 33 MHz, 48 I/O lines, a 16-bit timer, a 16-channel/10-bit analogue-to-digital converter and four serial communication channels. It may be mentioned here that the above-mentioned values are the maximum available ones across the family of devices.

2. MCORE Family of Microcontrollers (Freescale Semiconductors)

This family of microcontrollers is built around a processing core known as the MCORE microRISC engine. The design of the core combines high performance with low power consumption, which makes the MCORE family of microcontrollers particularly suitable for battery-operated and mobile applications. Salient features of this family of microcontrollers are as follows.

The family offers 32-bit wide load/store architecture, 16-bit wide instructions for fast instruction throughput between the core and the memory, 32 general-purpose registers and a four-stage instruction pipeline that facilitates most instructions to be completed in one clock cycle.

Other features include 32K of RAM, 256K of flash, 33 MHz of clock speed, two serial communication channels, 104 I/O lines, an eight-channel analogue-to-digital converter and two timers. Again, the above-mentioned values are the maximum available ones across the family of devices.

3. MPC500 Family of Microcontrollers (Freescale Semiconductors)

The MPC500 family of microcontrollers is configured around a 32-bit PowerPC core. Different members of the family include MPC555, MPC556, MPC561, MPC562, MPC563, MPC564, MPC565 and MPC566. PowerPC architecture based design provides compatibility with the PowerPC instruction set, including floating-point operations.

Salient features include 36K of RAM, 1024K of flash, a 66 MHz clock, three serial communication channels, 101 I/O lines, 40 channels of analogue-to-digital conversion and 70 timer channels. These microcontrollers are particularly suitable for scientific applications requiring complex operations.

4. MCFXXX Family of Microcontrollers (Freescale Semiconductors)

The MCFXXX family of microcontrollers is configured around a ColdFire Version 2 core. Different members of the family include MCF5206, MPC5207, MPC5208, MPC5211, MPC5212, MPC5213, MPC5214, MPC5216, MPC5232, MPC5233, MPC5234, MPC5235, MPC5249, MPC5270, MPC5271, MPC5272, MPC5274, MPC5275, MPC5280, MPC5281, MPC5282, MPC5327, MPC5328 and MPC5329. The core uses variable-instruction-length RISC architecture.

ColdFire instructions, which are similar to those in the 680X0 instruction set, are processed in a pipelined architecture of fetch and decode/execute units. The core also contains an enhanced multiply-and-accumulate (eMAC) unit, which has been designed to support DSP applications.

Other features include 64K of RAM, 66 MHz of clock, 5 serial communication channels, including an I2C bus and CAN support, 150 I/O lines and four timer channels. Again, the above-mentioned values are the maximum available ones across the family of devices.

5. LPC3000 Family of Microcontrollers (Philips Semiconductors)

The LPC-3000 family of 32-bit microcontrollers is based on Philips’ Nexperia platform. It is configured around an ARM926EJ core with the VFP9 floating-point coprocessor. The family offers enhanced signal-processing performance with the 926EJ core equipped with features such as single-cycle multiply-accumulate packed data and saturating arithmetic. The vector coprocessor is a high-speed floating-point unit and is IEEE754 compliant.

The LPC3000 family of microcontrollers incorporates 32K of instruction cache and 32K of data cache, which operate concurrently owing to the use of Harvard architecture. The family combines high performance with low power dissipation, which is made possible by its low-voltage operation at 1.2 V. It operates at clock speeds in excess of 200 MHz and supports a wide range of peripherals.

As an example, LPC3180 (the first member of the LPC3000 family of microcontrollers) has multiple serial interfaces including seven UARTs, two single master I2C interfaces and two SPI controllers, USB on-the-go, a 32-bit general-purpose timer with a 16-bit prescaler with capture and compare capability, a watchdog timer, PWM blocks with an output rate of up to 50 kHz and up to 55 general-purpose I/O pins.

6. TRICORETM Family of Microcontrollers (Infineon)

The TRICORE family of 32-bit microcontrollers uses a unified, single-core 32-bit microcontroller– DSP architecture optimized for real-time embedded systems. The architecture combines the real-time capability of a microcontroller with the computational power of a DSP and the high performance features of RISC load/store architecture.

The TRICORE family of microcontrollers offers various subfamilies, which include the AUDO-NextGeneration family, the AUDO1 family, the TC116X family and the TC1130 family. The family offers clock speeds ranging from 40 MHz (AUDO1 family) to 150 MHz (AUDO NextGeneration family) and is equipped with almost every microcontroller-related and peripheral-related features in terms of on-chip memory, power-saving modes, serial interfaces, counters/timers, PWM blocks, I/O ports, A/D converters and so on.

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