ECL Logic Family

The ECL family is the fastest logic family in the group of bipolar logic families. The characteristic features that give this logic family its high speed or short propagation delay are outlined as follows:

It is a non-saturating logic. That is, the transistors in this logic are always operated in the active region of their output characteristics. They are never driven to either cut-off or saturation, which means that logic LOW and HIGH states correspond to different states of conduction of various bipolar transistors.
The logic swing, that is, the difference in the voltage levels corresponding to logic LOW and HIGH states, is kept small (typically 0.85 V), with the result that the output capacitance needs to be charged and discharged by a relatively much smaller voltage differential.
The circuit currents are relatively high and the output impedance is low, with the result that the output capacitance can be charged and discharged quickly.

Subfamilies of ECL Logic Family

Different subfamilies of ECL logic include MECL-I, MECL-II, MECL-III, MECL 10K, MECL 10H and MECL 10E (ECLinPS^TM and ECLinPS Lite^TM).

MECL-I, MECL-II and MECL-III Series: MECL-I was the first monolithic emitter coupled logic family introduced by ON Semiconductor (formerly a division of Motorola SPS) in 1962. It was subsequently followed up by MECL-II in 1966. Both these logic families have become obsolete and have been replaced by MECL-III (also called the MC1600 series) introduced in 1968.

Although, chronologically, MECL-III was introduced before the MECL-10K and MECL-10H families, it features higher speed than both of its successors. With a propagation delay of the order of 1 ns and a flip-flop toggle frequency of 500 MHz, MECL-III is used in high-performance, high-speed systems.

The basic characteristic parameters of MECL-III are as follows:

gate propagation delay = 1 ns; output edge speed (indicative of the rise and fall time of output transition) = 1 ns; flip-flop toggle frequency = 500 MHz;
power dissipation per gate = 50 mW; speed–power product = 60 pJ;
input voltage = 0 – V_EE (V_EE is the negative supply voltage); negative power supply range (for V_CC = 0) = −5.1V to −5.3 V;
continuous output source current (max.) = 40 mA; surge output source current (max.) = 80 mA;
operating temperature range = −30 °C to +85 °C.

MECL-10K Series: The MECL-10K family was introduced in 1971 to meet the requirements of more general-purpose highspeed applications. Another important feature of MECL-10K family devices is that they are compatible with MECL-III devices, which facilitates the use of devices of the two families in the same system.

The increased propagation delay of 2 ns in the case of MECL-10K comes with the advantage of reduced power dissipation, which is less than half the power dissipation in MECL-III family devices.

The basic characteristic parameters of MECL-10K are as follows:

gate propagation delay = 2 ns (10100-series) and 1.5 ns (10200-series); output edge speed = 3.5 ns (10100-series) and 2.5 ns (10200- series);
flip-flop toggle frequency = 125 MHz (min.) in the 10100-series and 200 MHz (min.) in the 10200-series;
power dissipation per gate = 25 mW;
speed–power product = 50 pJ (10100-series) and 37 pJ (10200-series);
input voltage = 0 – V_EE(V_EE is the negative supply voltage); negative power supply range (for V_CC = 0) = −4.68 to −5.72 V;
continuous output source current (max.) = 50 mA; surge output source current (max.) = 100 mA;
operating temperature range = −30 °C to +85 °C.

MECL-10H Series: The MECL-10H family, introduced in 1981, combines the high speed advantage of MECL-III with the lower power dissipation of MECL-10K. That is, it offers the speed of MECL-III with the power economy of MECL-10K. Backed by a propagation delay of 1 ns and a power dissipation of 25 mW per gate, MECL-10H offers one of the best speed–power product specifications in all available ECL subfamilies.

Another important aspect of this family is that many of the MECL-10H devices are pinout/functional replacements of MECL-10K series devices, which allows the users or the designers to enhance the performance of existing systems by increasing speed in critical timing areas.

The basic characteristic parameters of MECL-10H are as follows:

gate propagation delay = 1 ns; output edge speed = 1 ns; flip-flop toggle frequency = 250 MHz (min.);
power dissipation per gate = 25 mW;
speed–power product = 25 pJ;
input voltage = 0 – V_EE (V_EE is the negative supply voltage); negative power supply range (for V_CC = 0) = −4.94 to −5.46 V;
continuous output source current (max.) = 50 mA; surge output source current (max.) = 100 mA;
operating temperature range = 0 °C to + 75 °C.

MECL-10E Series (ECLinPS^TM and ECLinPSLite^TM): The ECLinPS^TM family, introduced in 1987, has a propagation delay of the order of 0.5 ns. ECLinPSLite^TMis a recent addition to the ECL family. It offers a propagation delay of the order of 0.2 ns. The ECLPro™ family of devices is a rapidly growing line of high-performance ECL logic, offering a significant speed upgrade compared with the ECLinPSLite^TM devices.

Logic Gate Implementation in ECL

OR/NOR is the fundamental logic gate of the ECL family. Figure 1 shows a typical internal schematic of an OR/NOR gate in the 10K-series MECL family. The circuit in essence comprises a differential amplifier input circuit with one side of the differential pair having multiple transistors depending upon the number of inputs to the gate, a voltage- and temperature-compensated bias network and emitter follower outputs.

The internal schematic of the 10H-series gate is similar, except that the bias network is replaced with a voltage regulator circuit and the source resistor R_EE of the differential amplifier is replaced with a constant current source.

Typical values of power supply voltages are V_CC = 0 and V_EE=−5.2 V. The nominal logic levels are logic LOW = logic ‘0’ = −1.75 V and logic HIGH = logic ‘1’ = −0.9 V, assuming a positive logic system. The circuit functions as follows.

The bias network configured around transistor Q6 produces a voltage of typically −1.29 V at its emitter terminal. This leads to a voltage of −2.09 V at the junction of all emitter terminals of various transistors in the differential amplifier, assuming 0.8 V to be the required forward-biased P–N junction voltage.

Now, let us assume that all inputs are in a logic ‘0’ state, that is, the voltage at the base terminals of various input transistors is −1.75 V. This means that the transistors Q1, Q2, Q3 and Q4 will remain in cut-off as their base-emitter junctions are not forward biased by the required voltage. This leads us to say that transistor Q7 is conducting, producing a logic ‘0’ output, and transistor Q8 is in cut-off, producing a logic ‘1’ output.

In the next step, let us see what happens if any one or all of the inputs are driven to logic ‘1’ status, that is, a nominal voltage of −0.9 V is applied to the inputs. The base-emitter voltage differential of transistors Q1 – Q4 exceeds the required forward-biasing threshold, with the result that these transistors start conducting.

This leads to a rise in voltage at the common-emitter terminal, which now becomes approximately −1.7 V as the common-emitter terminal is now 0.8 V more negative than the base-terminal voltage. With rise in the common-emitter terminal voltage, the base-emitter differential voltage of Q5 becomes 0.31 V, driving Q5 to cut-off. The Q7 and Q8 emitter terminals respectively go to logic ‘1’ and logic ‘0’. This explains how this basic schematic functions as an OR/NOR gate.

We will note that the differential action of the switching transistors (where one section is ON while the other is OFF) leads to simultaneous availability of complementary signals at the output.

salient features of ecl logic family — Fig. 2

Figure 2 shows the circuit symbol and switching characteristics of this basic ECL gate. It may be mentioned here that positive ECL (called PECL) devices operating at +5 V and ground are also available. When used in PECL mode, ECL devices must have their input/output DC parameters adjusted for proper operation. PECL DC parameters can be computed by adding ECL levels to the new VCC.

We will also note that voltage changes in ECL are small, largely governed by VBE of the various conducting transistors. In fact, the magnitude of the currents flowing through various conducting transistors is of greater relevance to the operation of the ECL circuits. It is for this reason that emitter coupled logic is also sometimes called current mode logic (CML).

Salient Features of ECL Logic Family

There are many features possessed by MECL family devices other than their high speed characteristics that make them attractive for many high-performance applications. The major ones are as follows:

ECL family devices produce the true and complementary output of the intended function simultaneously at the outputs without the use of any external inverters. This in turn reduces package count, reduces power requirements and also minimizes problems arising out of time delays that would be caused by external inverters.
The ECL gate structure inherently has high input impedance and low output impedance, which is very conducive to achieving large fan-out and drive capability.
ECL devices with open emitter outputs allow them to have transmission line drive capability. The outputs match any line impedance. Also, the absence of any pull-down resistors saves power.
ECL devices produce a near-constant current drain on the power supply, which simplifies power supply design.
On account of the differential amplifier design, ECL devices offer a wide performance flexibility, which allows ECL circuits to be used both as linear and as digital circuits.
Termination of unused inputs is easy. Resistors of approximately 50 kΩ unused inputs to remain unconnected.

ECL Logic Family

ECL Logic Family

Subfamilies of ECL Logic Family

Logic Gate Implementation in ECL

Salient Features of ECL Logic Family

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